Re: [PATCH] perf_events: AMD event scheduling (v3)

[Stephane Eranian]

On Wed, Feb 10, 2010 at 12:59 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> On Mon, 2010-02-08 at 17:17 +0200, Stephane Eranian wrote:
>> Â Â Â Â This patch adds correct AMD Northbridge event scheduling.
>> Â Â Â Â It must be applied on top tip-x86 + hw_perf_enable() fix.
>>
>> Â Â Â Â NB events are events measuring L3 cache, Hypertransport
>> Â Â Â Â traffic. They are identified by an event code Â>= 0xe0.
>> Â Â Â Â They measure events on the Northbride which is shared
>> Â Â Â Â by all cores on a package. NB events are counted on a
>> Â Â Â Â shared set of counters. When a NB event is programmed
>> Â Â Â Â in a counter, the data actually comes from a shared
>> Â Â Â Â counter. Thus, access to those counters needs to be
>> Â Â Â Â synchronized.
>>
>> Â Â Â Â We implement the synchronization such that no two cores
>> Â Â Â Â can be measuring NB events using the same counters. Thus,
>> Â Â Â Â we maintain a per-NB * allocation table. The available slot
>> Â Â Â Â is propagated using the event_constraint structure.
>>
>> Â Â Â Â The 2nd version takes into account the changes on how
>> Â Â Â Â constraints are stored by the scheduling code.
>>
>> Â Â Â Â The 3rd version fixes formatting issues, code readability
>> Â Â Â Â and one bug in amd_put_event_constraints().
>>
>> Â Â Â Â Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>
>
> OK, took this with the below merged in.
>
> ---
> Index: linux-2.6/arch/x86/kernel/cpu/perf_event.c
> ===================================================================
> --- linux-2.6.orig/arch/x86/kernel/cpu/perf_event.c
> +++ linux-2.6/arch/x86/kernel/cpu/perf_event.c
> @@ -81,7 +81,7 @@ struct event_constraint {
> Â};
>
> Âstruct amd_nb {
> - Â Â Â int nb_id; Â/* Northbridge id */
> + Â Â Â int nb_id; Â/* NorthBridge id */
> Â Â Â Âint refcnt; /* reference count */
> Â Â Â Âstruct perf_event *owners[X86_PMC_IDX_MAX];
> Â Â Â Âstruct event_constraint event_constraints[X86_PMC_IDX_MAX];
> @@ -2268,7 +2268,7 @@ static inline int amd_is_nb_event(struct
> Â Â Â Âu64 val = hwc->config & K7_EVNTSEL_EVENT_MASK;
> Â Â Â Â/* event code : bits [35-32] | [7-0] */
> Â Â Â Âval = (val >> 24) | (val & 0xff);
> - Â Â Â return val >= 0x0e0;
> + Â Â Â return val >= 0xe00;
> Â}
>
I don't understand the change from 0xe0 to 0xe00.
That's not the same thing at all.
Event select is bits 0-7 + 32-35.
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