Re: [RFC PATCH 2/8] jump label v4 - x86: Intr oduce generic jump patching without stop_machine

[H. Peter Anvin]

If single-byte updates weren't atomic, then the int3 scheme would not be possible in the first place.  Of course, if you want there to be a synchronization point beyond which the modification is guaranteed to have affected all CPUs, you need an IPI-IRET on all CPUs.

The other thing to watch out for is that the CPU itself is subject to text modification through a different alias, which means some of the hardware SMC protections are ineffective.

"Mathieu Desnoyers" <mathieu.desnoyers@xxxxxxxxxx> wrote:

>* H. Peter Anvin (hpa@xxxxxxxxx) wrote:
>> On 01/14/2010 07:32 AM, Steven Rostedt wrote:
>> >> +
>> >> +	/* Replacing 1 byte can be done atomically. */
>> >> +	if (unlikely(len <= 1))
>> >> +		return text_poke(addr, opcode, len);
>> > 
>> > This part bothers me. The text_poke just writes over the text directly
>> > (using a separate mapping). But if that memory is in the pipeline of
>> > another CPU, I think this could cause a GPF.
>> > 
>> 
>> Could you clarify why you think that?
>
>Basically, what Steven and I were concerned about in this particular
>patch version is the fact that this code took a "shortcut" for
>single-byte text modification, thus bypassing the int3-bypass scheme
>altogether.
>
>As mere atomicity of the modification is not the only concern here
>(because we also have to deal with instruction trace cache coherency and
>so forth), then the int3 breakpoint scheme is, I think, also needed for
>single-byte updates.
>
>Thanks,
>
>Mathieu
>
>> 
>> 	-hpa
>> 
>> -- 
>> H. Peter Anvin, Intel Open Source Technology Center
>> I work for Intel.  I don't speak on their behalf.
>> 
>
>-- 
>Mathieu Desnoyers
>OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

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