Re: [PATCH] pata_hpt3x2n: fix overclocked MWDMA0 timing

[Jeff Garzik]

On 11/27/2009 02:47 PM, Sergei Shtylyov wrote:
> Hello, I wrote:
>
> > > Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@xxxxxxxxx>
> > > ---
> > > Sergei, XFER_UDMA_5 timing also looks suspicious,
> > > please take a look when you have a minute, thanks.
>
> > Yeah, but it's the same as XFER_UDMA_4, so actually underclocked...
> > However, it matches what the HPT371N datasheet and the vendor drivers
> > have. The 'hpt366' driver uses more speedy mode, with 22.5 ns cycle. ;-)
>
> I have just verified: this driver has always used this timing
> historically, at least for HPT372+ chips.

Could you clarify which "this timing" you are referring to?  :)  I never 
saw an Acked-by on this one.

	Jeff




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