Re: [PATCH 5/6] hw-breakpoints: Arbitrate access to pmu followingregisters constraints

[Benjamin Herrenschmidt]

On Thu, 2009-11-12 at 16:54 +0100, Frederic Weisbecker wrote:
> >  - On one embedded core at least we have a case where the core has 4
> > threads, but the data (4) and instruction (2) breakpoint registers are
> > shared. The 'enable' bits are split so a given data breakpoint can be
> > enabled only on some HW threads but that's about it.
> > 
> > I'm not sure if there's a realistic way to handle the later constraint
> > though other than just not allowing use of the HW breakpoint function on
> > those cores at all.
> > 
> > Ben.
> 
> 
> Yeah this latter one is tricky. Not sure how to handle it either.
> How are these hw-threads considered by the kernel core? As different
> cpu? 

Yes.

So it basically looks like you have 4 data and 2 HW instruction breakpoint
registers shared by 4 CPUs in a group :-)

Cheers,
Ben.


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