[tip:x86/pat] x86: Relegate CONFIG_PAT and CONFIG_MTRR configurability to EMBEDDED
From: tip-bot for Arjan van de Ven
Date: Mon Oct 12 2009 - 07:12:25 EST
Commit-ID: c03cb3149daed3e411657e3212d05ae27cf1a874
Gitweb: http://git.kernel.org/tip/c03cb3149daed3e411657e3212d05ae27cf1a874
Author: Arjan van de Ven <arjan@xxxxxxxxxxxxx>
AuthorDate: Sun, 11 Oct 2009 10:33:02 -0700
Committer: Ingo Molnar <mingo@xxxxxxx>
CommitDate: Mon, 12 Oct 2009 13:06:57 +0200
x86: Relegate CONFIG_PAT and CONFIG_MTRR configurability to EMBEDDED
MTRR and PAT support (which got added to CPUs over 10 years ago)
are no longer really optional in that more and more things are
depending on PAT just working, including various drivers and newer
versions of X. (to not even speak of MTRR)
Having this as a regular config option just no longer makes sense.
This patch relegates CONFIG_X86_PAT to the EMBEDDED category so
ultra-embedded can still disable it if they really need to.
Also-Suggested-by: Roland Dreier <rdreier@xxxxxxxxx>
Signed-off-by: Arjan van de Ven <arjan@xxxxxxxxxxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: Henrique de Moraes Holschuh <hmh@xxxxxxxxxx>
LKML-Reference: <20091011103302.62bded41@xxxxxxxxxxxxx>
Signed-off-by: Ingo Molnar <mingo@xxxxxxx>
---
arch/x86/Kconfig | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c876bac..a67363b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1321,7 +1321,9 @@ config MATH_EMULATION
kernel, it won't hurt.
config MTRR
- bool "MTRR (Memory Type Range Register) support"
+ bool
+ default y
+ prompt "MTRR (Memory Type Range Register) support" if EMBEDDED
---help---
On Intel P6 family processors (Pentium Pro, Pentium II and later)
the Memory Type Range Registers (MTRRs) may be used to control
@@ -1387,7 +1389,8 @@ config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT
config X86_PAT
bool
- prompt "x86 PAT support"
+ default y
+ prompt "x86 PAT support" if EMBEDDED
depends on MTRR
---help---
Use PAT attributes to setup page level cache control.
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