Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment baseis cache aligned

From: H. Peter Anvin
Date: Thu Sep 03 2009 - 16:36:42 EST

On 09/03/2009 01:03 PM, tip-bot for Jeremy Fitzhardinge wrote:
> Commit-ID: 1ea0d14e480c245683927eecc03a70faf06e80c8
> Gitweb:
> Author: Jeremy Fitzhardinge <jeremy@xxxxxxxx>
> AuthorDate: Thu, 3 Sep 2009 12:27:15 -0700
> Committer: Ingo Molnar <mingo@xxxxxxx>
> CommitDate: Thu, 3 Sep 2009 21:30:51 +0200
> x86/i386: Make sure stack-protector segment base is cache aligned
> The Intel Optimization Reference Guide says:
> In Intel Atom microarchitecture, the address generation unit
> assumes that the segment base will be 0 by default. Non-zero
> segment base will cause load and store operations to experience
> a delay.
> - If the segment base isn't aligned to a cache line
> boundary, the max throughput of memory operations is
> reduced to one [e]very 9 cycles.
> [...]
> Assembly/Compiler Coding Rule 15. (H impact, ML generality)
> For Intel Atom processors, use segments with base set to 0
> whenever possible; avoid non-zero segment base address that is
> not aligned to cache line boundary at all cost.
> We can't avoid having a non-zero base for the stack-protector
> segment, but we can make it cache-aligned.

With the new zero-based percpu segment, it seems we should be able to
subsume the stack protector into the percpu segment and reference both
via %gs -- we just have to reserve the first 24 bytes of the segment,
and being able to reduce the number of segments we need in the kernel is
good for multiple reasons.

Tejun - am I missing something why that would be hard or impossible?

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