Re: [VIA Support] Instruction timing and cache coherency issues

[Harald Welte]

On Thu, Jul 30, 2009 at 11:08:04AM +0200, Pavel Machek wrote:

> > Diddling with the things I have found that either "fix" or "work around"
> > the various timing / cache coherency issues - - -
> > Aw, so - found how to affect the timing issues sufficiently so that Linux
> > would panic dump rather than deadlock on the troublesum combination - -
> > *Functionally the same* panic backtrace that FreeBSD is showing.
> > 
> > @H.W.  Download the FreeBSD-8.0-beta2 and try running it on your Cloudbook
> > and HP-2133, you can see what is happening.  Then you might have a word or
> > two with the silicon growers.
> > 
> So... you believe you have pinpointed bug in their cpu design?

I would not preclude that, but I think what might be more likely is that there
is some difference between how Intel and how VIA/Centaur behaves in a certain
situation, or the compiler making a wrong assumption about what it can do or
cannot do (remember e.g. for the VIA C3 there was no cmpxchg8, but gcc uses
it in case you compile with i686 optiomization).

I have not yet tried FreeBSD 8 on the cloudbook, but expect to have time during
the next days.  However, since I am not familiar with the FreeBSD kernel
architecture, I would definitely prefer something where I can reproduce the
problem on Linux.

Michael has indicated that he can now crash (oops) the kernel rather than deadlock.
With which kernel is that?  I would love to give that one a try.

-- 
- Harald Welte <HaraldWelte@xxxxxxxxxxx>	    http://linux.via.com.tw/
============================================================================
VIA Free and Open Source Software Liaison
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