Re: [PATCH 2/9] add support for the TI VLYNQ bus

[Florian Fainelli]

Le Tuesday 02 June 2009 07:08:54 Andrew Morton, vous avez écrit :
> On Mon, 1 Jun 2009 13:58:27 +0200 Florian Fainelli <florian@xxxxxxxxxxx> 
wrote:
> > This patch adds support for the TI VLYNQ high-speed,
> > serial and packetized bus. This bus allows external
> > devices to be connected to the System-on-Chip and
> > appear in the main system memory just like any memory
> > mapped peripheral. It is widely used in TI's networking
> > and mutlimedia SoC, including the AR7 SoC.
> >
> >
> > ...
> >
> > +struct vlynq_regs {
> > +	u32 revision;
> > +	u32 control;
> > +	u32 status;
> > +	u32 int_prio;
> > +	u32 int_status;
> > +	u32 int_pending;
> > +	u32 int_ptr;
> > +	u32 tx_offset;
> > +	struct vlynq_mapping rx_mapping[4];
> > +	u32 chip;
> > +	u32 autonego;
> > +	u32 unused[6];
> > +	u32 int_device[8];
> > +};
> > +
> > +#define vlynq_reg_read(reg) readl(&(reg))
> > +#define vlynq_reg_write(reg, val)  writel(val, &(reg))
>
> grumble.  These just make the code harder to follow.  it'd be better to
> open-code readl() and writel() at the callsites.

I do not understand how to fix this. Would an inlined accessors be a better 
solution for you?

Thanks.
-- 
Best regards, Florian Fainelli
Email : florian@xxxxxxxxxxx
http://openwrt.org
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