[PATCH 0/29] x86/perfcounters: x86 and AMD cpu updates

[Robert Richter]

This patch series updates the perfcounters implementation mainly for
the x86 architecture.

Also, it introduces a data structure (struct pmu) describing a generic
performance monitoring unit (pmu). This structure is a replacement for
struct hw_perf_counter_ops. Similiar, I introduced struct x86_pmu for
the x86 architecture (as a replacement for struct pmc_x86_ops).

There are patches for x86 with some fixes and cleanups, a change in
the model specific split and a complete rework of AMD pmu code. The
result is simplified model specific code and more generalized and
unified code. Features that are only supported by AMD or Intel are now
implemented in vendor specific functions.

The AMD pmu differs to Intel, especially there is no status register
and also there are no fixed counters. This makes a separate interrupt
handler for AMD cpus necessary. Also, a global disable/enable of the
performance counters (e.g. to avoid NMIs to protect the modification
of a list) is expensive on AMD cpus leading to up to 4 msr
reads/writes per counter. There is still some more work to do here to
avoid this.

This patch series bases on the tip/percounters/core branch.

I developed this patches based on 03ced43 and later rebased to
1b88991. The latest tip/percounters/core branch seems to be broken, no
nmis are delivered, only perfcounter interrupts with no results on
kerneltop. I am still debugging this. However, I could test
successfully the patch series based on 03ced43 and want to release the
patches anyway.

-Robert



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