Re: [RFC v2] virtio: add virtio-over-PCI driver

[Grant Likely]

On Tue, Apr 14, 2009 at 3:52 PM, David Hawkins <dwh@xxxxxxxxxxxxxxxx> wrote:
> Hi Grant,
>
>> Thanks David.  I haven't looked closely at the xilinx pci data sheet
>> yet, but I don't expect too many issues in this area.  As you say, it
>> won't take much to code it up.  I'll be poking my VHDL engineer to
>> make it do what I want it to.  :-)
>
> The key aspects of the core will be that it is Master/Target
> so that it can take over the PCI bus, and that it has a
> DMA engine that can take care of most of the work. In
> your case, since you have a DMA controller on the host
> (MPC5200) and the target (Xilinx), your driver might end
> up having nicer symmetry than our application. The
> most efficient implementation will be the one that
> uses PCI writes, i.e., MPC5200 DMAs to the Xilinx core,
> and the Xilinx core DMAs to the MPC5200.

Hmmm, I hadn't thought about this.  I was intending to use the
Virtex's memory region for all virtio, but if I can allocate memory
regions on both sides of the PCI bus, then that may be best.

> If you use
> a PCI Target only core, then the MPC5200 DMA controller
> will have to do all the work, and read transfers might
> be slightly less efficient.

I'll definitely intend to enable master mode on the Xilinx PCI controller.

> Our target boards (PowerPC) live in compactPCI backplanes
> and talk to x86 boards that do not have DMA controllers.
> So the PCI target board DMA controllers are used to
> transfer data efficiently to the x86 host (writes)
> and less efficiently from the host to the boards
> (reads). Our bandwidth requirements are 'to the host',
> so we can live with the asymmetry in performance.

Fortunately I don't have very high bandwidth requirements for the
first spin, so I have some room to experiment.  :-)

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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