Jeremy Fitzhardinge wrote:H. Peter Anvin wrote:In this particular case, this is actually false. "No PAT" in the processor is *not* the same thing as "no cacheability controls in the page tables". Every processor since the 386 has had UC, WT, and WB controls in the page tables; PAT only added the ability to do WC (and WP, which we don't use). Since the number of processors which can do WC at all but don't have PAT is a small set of increasingly obsolete processors, we may very well choose to simply ignore the WC capabilities of these particular processors.
I'm not quite sure what you're referring to with "this is actually false". Certainly we support cachability control in ptes under Xen. We just don't support full PAT because Xen uses PAT for itself.
What do you define as "full PAT"? If what you mean is that Xen lays claims to the PAT MSR and only allows a certain mapping that's hardly a problem... other than that it's not an exhaustible resource so I guess I really don't understand what you're trying to say here.