Re: [PATCH 45/79] [PATCH] fix apic acking of irqs
From: Glauber Costa
Date: Thu Mar 20 2008 - 11:09:20 EST
Maciej W. Rozycki wrote:
On Wed, 19 Mar 2008, Glauber de Oliveira Costa wrote:
EOI is a write-only register. Using write around will have the effect
of reading it, which will make all subsequent reads of the ESR register
to return an error code. It was unnotices for quite a while because main sources
of reading the ESR register where done prior to apic interrupt enabling.
Are you sure this actually triggers for APIC chips affected by the
erratum in question? And please note that for them the effect of two
consecutive writes will be much more disastrous than setting a bit in the
ESR register.
Maciej
I'm not _sure_, but I can't find anything in the errata list that states
otherwise. It would be great that anyone has such a system to test it.
But with the current conditions, it will break bootup code. In case it
is really a problem, we'd need to make a special case for that.
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