Re: ehci-hcd affects hda speed

From: Rene Herman
Date: Mon Mar 17 2008 - 19:23:08 EST


On 17-03-08 22:00, David Brownell wrote:

On 15-03-08 23:46, Lev A. Melnikovsky wrote:

changing the bit 5 (EHCI sleep time select: 0=1us 1=10us)
of register 0x4B seems to resolve my own problem.

Note that 10 usec is the value used in the EHCI spec.

And yes, waiting only 1 usec between schedule scans is
absolutely certain to hammer on the PCI bus quite rudely,
preventing other devices from getting Real Work done.

Could someone put together an EHCI patch to make sure
that bit is set on vt6212 parts? For the VT8235 that
register seems to be marked (in an old document someone
forwarded to me) as "reserved, do not program"; so this
should be specific to vt6212 EHCI. (PCI vendor 0x1106,
device 0x3104, revision 0x60 ... the revision being what
says "vt6212" vs "vt8235" or "vt8237" etc.

Just something like this? Completely untested as I've not the hardware anymore. Googling for an old lspci, I had a revision 0x63, and Lev has a revision 0x65. The VT6212(L) should be 0x60+ it seems.

The "CC:" should be a "Tested-by:" if that's actually the case.

But yes, as he also asked, should this be the fix at all?

Rene. commit fb221b24a314069af26db8c9beb6c843efcafa38
Author: Rene Herman <rene.herman@xxxxxxxxx>
Date: Tue Mar 18 00:02:16 2008 +0100

USB: VIA VT6212 10us EHCI sleep time select

The VIA VT6212 uses a 1us EHCI sleep time by default which
hammers the PCI bus bad. Use the 10us spec value instead
as suggested by Lev A. Melnikovsky.

CC: Lev A. Melnikovsky <melnikovsky@xxxxxxx>
Signed-off-by: Rene Herman <rene.herman@xxxxxxxxx>

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 3ba0166..35a6ccb 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -152,6 +152,15 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
break;
}
break;
+ case PCI_VENDOR_ID_VIA:
+ if (pdev->device == 0x3104 && pdev->revision >= 0x60) {
+ u8 tmp;
+
+ /* VT6212: EHCI sleep time 10us (default 1) */
+ pci_read_config_byte(pdev, 0x4b, &tmp);
+ pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
+ }
+ break;
}

ehci_reset(ehci);