Re: [PATCH] x86: use explicit timing delay for pit accesses in kerneland pcspkr driver

[H. Peter Anvin]

Rene Herman wrote:
> On 18-02-08 23:07, Rene Herman wrote:
>
> > On 18-02-08 23:01, H. Peter Anvin wrote:
> >
> > > Rene Herman wrote:
> > > > Yes, but generally not any P5+ system is going to need the PIT delay 
> > > > in the first place meaning it just doesn't matter. There were the 
> > > > VIA issues with the PIC but unless I missed it not with the PIT.
> > >
> > > Uhm, I'm not sure I believe that's safe.
> > >
> > > The PIT is particularly pissy in this case -- the semantics of the 
> > > PIT are ill-defined if there hasn't been a PIT clock between two 
> > > adjacent accesses, so I fully expect that there are chipsets out 
> > > there which will do very bad things in this case.
> >
> > Okay. Now that they're isolated, do you have a suggestion for 
> > {in,out}b_pit? You say a PIT clock, so do you think we can bounce of 
> > the PIT iself in this case after all?
>
> Am I correct that channel 1 is never used? A simple read from 0x41?

Channel 1 is available for the system.  In modern systems, it's pretty 
much available for the OS, although that's never formally stated (in the 
original PC, it was used for DRAM refresh.)

However, I could very easily see a chipset have issues with that kind of 
stuff.

	-hpa
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