I believe this will suffer from the issue that was raised: this will use
udelay() long before loop calibration (and no, we can't just "be conservative" since there is no "conservative" value we can use.)
Worse, I suspect that at least the PIT, which may need to be used for udelay calibration, is one of the devices that may be affected. I have seen the Verilog for a contemporary chipset, and it can only access the PIT once per microsecond -- this actually has to do with the definition of the PIT; some of the PIT operations are ill-defined if allowed at a higher frequency than the PIT clock.