Re: [patch] x86: improved memory barrier implementation
From: Linus Torvalds
Date: Fri Sep 28 2007 - 12:15:55 EST
On Fri, 28 Sep 2007, Alan Cox wrote:
> - You've not shown the patch has any performance gain
It would be nice to see this.
> - You've probably broken Pentium Pro
Probably not a big deal, but yeah, we should have that broken-ppro option.
> - and for modern processors its still not remotely clear your patch is
> correct because of NT stores.
This one I disagree with. The *old* code doesn't honor NT stores *either*.
The fact is, if you use NT stores and then depend on ordering, it has
nothing what-so-ever to do with spinlocks or smp_[rw]mb. You need to use
the DMA barriers (ie the non-smp ones).
The non-temporal stores should be basically considered to be "IO", not any
normal memory operation.
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