Re: [PATCH] i386: add command line option"local_apic_timer_c2_ok"

[Mark Langsdorf]

Andi Kleen wrote:
> "Langsdorf, Mark" <mark.langsdorf@xxxxxxx> writes:
>
> > > > If we really care about using the LAPIC timer on systems with deeper
> > > > than C1 support, the only alternative seems to be to test
> > > > if it actually works or not at boot and run-time.
> > > > Otherwise, we wait for future hardware with guaranteed
> > > > not to break under any (BIOS) conditions ships, and check for that.
> > > >
> > > > Based on what I read of the HP nx6325 where the LAPIC timer
> > > > is breaking C1, AMD is in the same boat.
> > > The nx6325 (Turion 64 X2) exports only C1.
> > > I'm not sure how the conclusion was drawn that it has
> > > a broken lapic timer as reflected in the "nolapic_timer" patch:
> > If both cores goes into C1 at the same time, the chipset
> > can move the processor into a C3 like state called C1e.
>
> ... and that seems to break the local APIC timer.

Yes.  The APIC timer still runs, but no longer has an HT link
to send the signal on.

> > AMD can craft a patch to sort this out as soon as we have
> > an idea what the framework is going to look like.
>
> Just a snippet to detect it would be great. Then the dmi scan
> could be removed and replaced with that. This would be a 2.6.21
> candidate imho over the DMI hack.

Reviewed but not tested.  Needs to be wrapped in an AMD specific
call.

#define ENABLE_C1E_MASK		0x18000000
#define CPUID_PROCESSOR_SIGNATURE	1
#define CPUID_XFAM		0x0ff00000
#define CPUID_XFAM_K8		0x00000000
#define CPUID_XFAM_10H		0x00100000
#define CPUID_XFAM_11H		0x00200000
#define CPUID_XMOD		0x000f0000
#define CPUID_XMOD_REV_F	0x00040000

	int safe_c1 = 1;
	u32 eax, lo, hi;
	eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE)
	switch (eax & CPUID_XFAM) {
	case CPUID_XFAM_K8:
		if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
			break;
	case CPUID_XFAM_10H:
	case CPUID_XFAM_11H:
		rdmsr(MSR_ENABLE_C1E, lo, hi);
		if (lo & ENABLE_C1E_MASK)
			safe_c1 = 0;
		break;
	default:
		/* err on the side of caution */
		safe_c1 = 0;
	}

-Mark Langsdorf
Operating Systems Research Center
AMD, Inc.


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