RE: [PATCH] i386: add command line option"local_apic_timer_c2_ok"

[Langsdorf, Mark]

> > If we really care about using the LAPIC timer on systems with deeper
> > than C1 support, the only alternative seems to be to test
> > if it actually works or not at boot and run-time.
> > Otherwise, we wait for future hardware with guaranteed
> > not to break under any (BIOS) conditions ships, and check for that.
> > 
> > Based on what I read of the HP nx6325 where the LAPIC timer
> > is breaking C1, AMD is in the same boat.
> 
> The nx6325 (Turion 64 X2) exports only C1.
> I'm not sure how the conclusion was drawn that it has
> a broken lapic timer as reflected in the "nolapic_timer" patch:

If both cores goes into C1 at the same time, the chipset
can move the processor into a C3 like state called C1e.
 
> +               /*
> +                * BIOS exports only C1 state, but uses deeper power
> +                * modes behind the kernels back.
> +                */
> +                 .callback = lapic_check_broken_bios,
> +                 .ident = "HP nx6325",
> +                 .matches = {
> +                       DMI_MATCH(DMI_PRODUCT_NAME, "HP 
> Compaq nx6325"),
> +                 },
> +        },
> 
> But if this is true, then I don't know how to determine on
> an AMD system if the LAPIC timer is guaranteed to work --
> even for systems with just C1.
> 
> Jordan, William, can you clarify?

For K7 and K8 through and including revision E, the LAPIC
timer is guaranteed to work in C1.

For K8 revisions F and G, and for upcoming family 0x10 and
0x11 parts, if either bit in MSRC001_0055[28:27] is set,
C1e is enabled and the LAPIC timer cannot be trusted in
C1.

AMD can craft a patch to sort this out as soon as we have
an idea what the framework is going to look like.

-Mark Langsdorf
Operating Systems Research Center
AMD, Inc.


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