Re: Opinion on ordering of writel vs. stores to RAM

[Michael Chan]

Benjamin Herrenschmidt wrote:
> > The tg3 bug actually seems not to be because of the missing wmb()'s,
> > [the driver and all net traffic survive just fine in the case of
non- 
> > TSO],
> > but just because of a plain-and-simple programming bug in the
driver.
> > I'll run some tests tomorrow to confirm.  If I'm right, this fix
should
> > go into .18 and into .17-stable at least.
> 
> Interesting :) I didn't actually verify the barrier problem theory
> (though the driver does indeed seem to lack them, so there _is_ a
> problem there too), I trusted Michael Chan who seemed to know about
the
> bug :) 

It definitely is caused by lack of memory barriers before the writel().
IBM, Anton, and all of us know about this.  TSO probably makes it more
susceptible because you write to many buffer descriptors before you
issue one writel() to DMA all the descriptors.  The large number of
TSO descriptors makes re-ordering more likely.

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