It needs there to be no bus mastering occuring at the timentions
of a CPU speed transition. Though I'm unable to find the part that me
this in the specs I have right now.
Dave
"Once this is set, the processor will switch to the
value in [26:23] on the next AUTOHALT transition. The duration of the A
UTOHALT
should be >=1ms to ensure the CPU's internal PLL is resynchronized. F
or AUTOHALT, this means interrupts must be disabled except for the time ti
ck, which should be reset to >=1ms. Care must be taken to avoid other sys
tem events that could interfere with this operation. A few examples are snooping, NMI, INIT, SMI and FLUSH."
For CPU's with Longhaul MSR this time is equal to 200us.