+config MPC8360E_PB
+ bool "Freescale MPC8360E PB"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This option enables support for the MPC836x EMDS Processor Board.
+
endchoice
I don't think this is really required option. I guess 836x + QUICC_ENGINE should
be enough (with a proviso that 8360 won't boot without qe.
We select a board and the board implies cpu family and soc feature. That will be better for users rather than expecting them to know the very detail.
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.cb/arch/powerpc/platforms/83xx/mpc8360e_pb.cnew file mode 100644No changelog entries for new files please... git tracks it good enough.
index 0000000..b4ddb0a
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@xxxxxxxxxxxxx>
+ * Yin Olivia <Hong-hua.Yin@xxxxxxxxxxxxx>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific routines.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
This is Freescale protocol. If it is not welcomed, we will change it.
I will move it.+#ifdef CONFIG_QUICC_ENGINEAnd if we have a design, which do not contain real ethernet UCC usage? Or UCC
+ qe_reset();
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+
+ /* Reset the Ethernet PHY */
+ bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
+ bcsr_regs[9] &= ~0x20;
+ udelay(1000);
+ bcsr_regs[9] |= 0x20;
+ iounmap(bcsr_regs);
+
geth is disabled somehow explicitly? Stuff like that normally goes to the
callback that is going to be triggered upon Etherbet init.