[PATCH] (Longhaul 1/5) PCI: Protect bus master DMA from Longhaulby rw semaphores

[Rafał Bilski]

> If I understand correctly, trouble occurs when the processor tries to
> snoop? Would disabling (via MSR) and flushing the caches before changing
> the frequency help in that case?
> 
> Groeten,
> Bart
> 

CPU is VIA C3 in EBGA "Nehemiah" core 6.9.8.
I'm using flush_cache_all(). Is there anything more powerfull?
I'm using MSR_VIA_FCR.
I can disable L2 cache (or at least I think so) - this doesn't help.
I can't disable L1 cache - processor stops when I'm trying to set 
I-cache or D-cache disable bit.

Thanks
Rafał


----------------------------------------------------------------------
PS. Fajny portal... >>> http://link.interia.pl/f196a

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/