Re: more smpnice patch issues

[Peter Williams]

Peter Williams wrote:
> Siddha, Suresh B wrote:
> > more issues with smpnice patch...
> >
> > a) consider a 4-way system (simple SMP system with no HT and cores) 
> > scenario
> > where a high priority task (nice -20) is running on P0 and two normal
> > priority tasks running on P1. load balance with smp nice code
> > will never be able to detect an imbalance and hence will never move 
> > one of the normal priority tasks on P1 to idle cpus P2 or P3.
>
> Why?

OK, I think I know why.  The load balancing code will always decide that 
P0 is the busiest CPU, right?

Peter
--
Peter Williams                                   pwil3058@xxxxxxxxxxxxxx

"Learning, n. The kind of ignorance distinguishing the studious."
 -- Ambrose Bierce
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