Re: [discuss] [patch] x86_64: align and pad x86_64 GDT on page boundary

From: Andi Kleen
Date: Sun Dec 11 2005 - 21:33:01 EST


On Sun, Dec 11, 2005 at 06:34:16PM -0800, Zwane Mwaikambo wrote:
> On Fri, 9 Dec 2005, Ravikiran G Thirumalai wrote:
>
> > > For the BP case it's ok as
> > > long as the beginning is correctly aligned and the rest
> > > is read-only.
> >
> > Just that any writes on the bp GDT will invalidate the idt_table cacheline,
> > which is read mostly (as Nippun pointed out). So could we keep the padding
> > as it is for the BP too?
>
> But how often is this occuring? I presume this is for the virtualisation

GDT writes happen often if you use threads with TLS.

> case only?

In this case for programs running on ScaleX86's hypervisor yes.

-Andi
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