Re: [RFC] AMD64 @ K8T800/VT8237: Doubled IOAPIC-level-interrupt rate

[Karsten Wiese]

Am Donnerstag, 4. August 2005 17:19 schrieb Ingo Molnar:
> 
> * Karsten Wiese <annabellesgarden@xxxxxxxx> wrote:
> 
> > Hi,
> > 
> > this should likely be addressed to VIA Taiwan,
> > but I don't know their engineer's e-mail address and their forum
> > doesn't work for me.
> > Maybe somebody here has a clue?
> > Or maybe this is even motherboard specific?
> > 
> > To reproduce:
> > 	$ aplay -Dhw:0 -fdat /dev/zero
> > 
> > On a sane system (or here in PIC Mode) you'll see
> > around 12 Interrupts/s.
> > Here I see 24.
> 
> i think this is an effect of the 'POST-flush' symptom: the IO-APIC write 
> of unmasking the IRQ does not reach the chipset before the ACK via the 
> local-APIC does. Does it work fine if you artificially read after the 
> IO-APIC write?
> 
Sorry, I missed to say this happens on mainline .12 and .13-rcx.
In i386 and x86_64 mode.
So there is no IO-APIC (un)masking during the interrupt Routine.

I printk()ed the CPU-APIC's IRR immediately before the soundcard's
interrupt pin is deasserted and immediately after that:
The relevant IRR-bit is set again just then!

    Karsten

	

	
		
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