Re: pci cacheline size / latency oddness.

[Parag Warudkar]

On Mon, 2005-08-01 at 19:35 -0400, Dave Jones wrote:
> This means we will do the wrong thing on AMD machines which have
> 64 byte cachelines.

pcibios_init (in i386/pci/common.c, which is linked in by X86_64 PCI
code) seems to do this 
 
if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
                pci_cache_line_size = 64 >> 2;  /* K7 & K8 */

Is it correct to expect all AMD k7/8 machines to have 16 as cache line
size - I thought 64 was more appropriate?

On my Athlon64 laptop, all PCI devices end up having 0 latency. 

> x86-64 doesn't have an arch override for pci_cache_line_size

I am trying to fix it up - What's the right way to override it in x86_64
code?  Just initialize it to 64 may be?

Parag


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