On Fri, Sep 10, 2004 at 02:49:15PM -0300, Marcelo Tosatti wrote:
Oops, right. wli's patch is borked for NUMA. Clamping it at 64 should
do fine.
No, it DTRT. Batching does not directly compensate for increases in
arrival rates, rather most directly compensates for increases to lock
transfer times, which do indeed increase on systems with large numbers
of cpus.
On Fri, Sep 10, 2004 at 02:56:11PM +1000, Nick Piggin wrote:
Secondly is that you'll might really start putting pressure on small L1
caches (eg. Itanium 2) if you bite off too much in one go. If you blow
it, you'll have to pull all the pages into cache again as you process
the pagevec.
On Fri, Sep 10, 2004 at 02:49:15PM -0300, Marcelo Tosatti wrote:
Whats the L1 cache size of Itanium2? Each page is huge compared to the pagevec
structure (you need a 64 item pagevec array on 64-bits to occupy the space of one 4KB page). So I think you wont blow up the cache even with a really big pagevec.
A 511 item pagevec is 4KB on 64-bit machines.