Re: [PATCH] cacheline align pagevec structure

[William Lee Irwin III]

On Thu, Sep 09, 2004 at 04:09:05PM -0700, William Lee Irwin III wrote:
>> Reducing arrival rates by an Omega(NR_CPUS) factor would probably help,
>> though that may blow the stack on e.g. larger Altixen. Perhaps
>> O(lg(NR_CPUS)), e.g. NR_CPUS > 1 ? 4*lg(NR_CPUS) : 4 etc., will suffice,
>> though we may have debates about how to evaluate lg(n) at compile-time...
>> Would be nice if calls to sufficiently simple __attribute__((pure))
>> functions with constant args were considered constant expressions by gcc.

On Thu, Sep 09, 2004 at 07:12:38PM -0300, Marcelo Tosatti wrote:
> Let me see if I get you right - basically what you're suggesting is 
> to depend PAGEVEC_SIZE on NR_CPUS?

Yes. The motive is that as the arrival rate is O(num_cpus_online()), and
NR_CPUS is supposed to be strongly correlated with that, so reducing the
arrival rate by a (hopefully) similar factor ought to help.


-- wli
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