Re: page fault scalability patch final : i386 tested, x86_64support added

[Paul Mackerras]

Andrew Morton writes:

> hm.  What's the maximum virtual size on power5?

The hardware MMU maps a full 64-bit effective address to a physical
address (one of the (few) advantages of using a hash table :).  That's
true on all the ppc64 processors.  I'm not sure how many bits of
physical address the power5 chip uses, but it is around 50.

Under Linux we are currently limited to a 41-bit virtual address space
(2TB) for user processes, because of the three-level page tables and
the 4kB page size (the pgd and pmd entries are 32 bits).  Due to
various things the linear mapping (and thus the amount of RAM we
can use) is currently also limited to 2TB.  We can increase that
without too much pain, and we'll have to do that at some stage (no one
has yet offered us a 2TB box to play with, but the time will come, for
sure :).

Regards,
Paul.

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