RE: MMCONFIG violates pci power mgmt spec

[Michael Chan]

> > For example, if the device is transitioning into or out of 
> D3hot, the 
> > spec requires a delay of 10 msec before any accesses can be made to 
> > the device. The dummy read in pci_mmcfg_write violates the delay 
> > requirements even though pci_set_power_state has all the necessary 
> > delays.
> 
> Interesting. What happens? Hangs? 
> 

What happens depends on the system/chipset/bios. Sometimes we see an
NMI, sometimes nothing bad happens.

> 
> Reading is the official way to flush.
> 

The MMCONFIG ECN document from pcisig below gives a few examples on how
the mmconfig write can be flushed. The exact mechanism of course is
implemention specific.

http://www.pcisig.com/specifications/pciexpress/specifications

Michael

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