MMCONFIG violates pci power mgmt spec

[Michael Chan]

We are encountering a problem with the MMCONFIG code with respect to
power management. Specifically, when pci_mmcfg_write is used to program
a PCI Express device's PMCSR to a different power state, the dummy read
at the end of that routine violates the transition delay specified in
the PCI power management spec.

For example, if the device is transitioning into or out of D3hot, the
spec requires a delay of 10 msec before any accesses can be made to the
device. The dummy read in pci_mmcfg_write violates the delay
requirements even though pci_set_power_state has all the necessary
delays.

I have contacted "Durairaj, Sundarapandian
<sundarapandian.durairaj@xxxxxxxxx>" but did not get a response, and so
I'm posting to this list. One question I wanted to ask him was whether
the dummy read was necessary. If the Intel chipset treats the mmconfig
write as a non-posted write, the dummy read becomes unnecessary and
removing it will solve the problem. If it is treated as a posted write,
I wonder if there is another way to flush it other than reading from the
target device.

Thanks,
Michael

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