Re: PAT support

[Albert Cahalan]

Eric W. Biederman writes:
> Andi Kleen <ak@xxxxxx> writes:

>> Yes agreed. I already had vendors complaining about this.
>> But for this it will need some more work - the MTRRs need to be fully
>> converted to PAT and then disabled (because MTRRs have 
>> higher priority than PAT). Doing so is a lot more risky than 
>> what Terrence's patch does currently though.  But longer term
>> we will need it.
>
> Ugh.  You are right.  The processors look at the two types and pick
> the one that caches the least.  So PAT can't enable caching :(

There's more to it than this. You need to use both
the MTRRs and PAT for best performance. I can't find
the explanation in my AMD manual, so maybe this is
an Intel-only thing. From (human) memory:

Use the PAT stuff as your primary cache-control
mechanism. Then, to the extent that you can, use
the MTRRs to double-mark some of the uncached or
uncachable memory. This avoids some sort of
useless bus traffic or TLB goings-on.

Sorry I can't be clearer; check the Intel books.



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