Re: [PATCH] speed up SATA

[Marc Bevand]

On 30 Mar 2004, Jeff Garzik wrote:
| Marc Bevand wrote:
| >I think I am reaching the physical limit of the PCI bus (theoretically it
| >would be 133 MB/s or 133000 blocks/s). When setting the PCI latency 
| >timer of
| >the SiI3114 controller to 240 (was 64), I am able to reach 100000 blocks/s.
| 
| That's interesting.
| 
| I wonder if we should look at making pci_set_master()'s latency timer 
| setting code be a bit smarter.

AFAIK choosing the optimal latency timer for each device on a PCI bus is
not a trivial thing, one needs to take into account a lots of things.
But making it a "bit smarter" would be "good enough".

| It (pcibios_set_master in arch/i386/pci/i386.c) current checks the 

Actually my arch is x86_64 ;-) But I guess the code is very similar.

| latency timer value programmed by the BIOS.  If the BIOS did not 
| initialize the value, then it is set to 64.  Otherwise, it is clamped to 
| the maximum 255.
| 
| I wonder if your BIOS shouldn't increase that latency timer value...?

My BIOS seems to always initialize the latency timer. There is a menu
in which one can choose the value (32, 64, 96, etc), and the default
setting (when "loading failsafe settings" or "loading optimized
settings") is 64 (that is where the value is coming from). The BIOS
does not offer an "auto" value that would be computed dynamically for
optimal performances.

-- 
Marc Bevand                          http://www.epita.fr/~bevand_m
Computer Science School EPITA - System, Network and Security Dept.
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