Re: problem with cache flush routine for G5?

From: Segher Boessenkool
Date: Mon Mar 08 2004 - 02:52:39 EST

After doing some digging in the 970fx specs, it seems that we may not need to explicitly force a store of the L1 dcache at all. According to the docs, the L1 dcache is unconditionally store-through. Thus, for a brute-force implementation we should be able to just invalidate the whole icache, do the appropriate sync/isync, and it should pick up the changed instructions from the L2 cache. Do you see any problems with this? Do I actually still need the store?

You need a sync instruction before the instruction cache invalidate,
to make sure all stores to L2 have completed.

I don't know which "970fx specs" you mean, but if it's the programming
manual, it should tell you how to invalidate the entire instruction
cache (and how to flush the L2 cache, if you really must. But just don't).


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