Re: Pentium M config option for 2.6

[Dave Jones]

On Sun, Jan 04, 2004 at 10:03:28AM -0500, Rob Love wrote:
 > On Sun, 2004-01-04 at 07:27, Mikael Pettersson wrote:
 > > And since P-M doesn't do SMP, does cache line size even
 > > matter? There are no locks to protect from ping-ponging.
 > 
 > Cache line size does still come into the picture on UP, albeit not as
 > much as with SMP - but e.g. it still matters to things like device
 > drivers doing DMA.

Regardless, Tomas's patch changed CONFIG_X86_L1_CACHE_SHIFT for
that CPU, and CONFIG_X86_L1_CACHE_SHIFT shouldn't affect this.
The cacheline size is determined at boottime using the code in
pcibios_init() and set using pci_generic_prep_mwi().

The config option is the default that pci_cache_line_size starts at,
but this gets overridden when the CPU type is determined.

		Dave

-- 
 Dave Jones     http://www.codemonkey.org.uk
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