Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Jamie Lokier]

Geert Uytterhoeven wrote:
> > BTW the 020/030 caches are VIVT (and also only writethrough), the 040/060 
> > caches are PIPT.
> 
> That explains a bit. But the '060 stores are coherent, while the '040 stores
> aren't.

The L1 cache is coherent on the '040 according to the results.  It's
the store buffer snooping which fails.  Presumably the CPU core is
looking ahead at recent writes comparing just virtual addresses.

-- Jamie
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