Re: about PENTIUM4 cache line

[David B. Stevens]

What's even more interesting is the following:

tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT 
(CONFIG_X86_L1_CACHE_SHIFT)
include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/asm/cache.h:#define L1_CACHE_SHIFT      (CONFIG_X86_L1_CACHE_SHIFT)
include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
tux:/usr/src/linux-2.6.0-test3 #

Life sure is interesting.

Cheers,
  Dave


Jamie Lokier wrote:
> michaelc wrote:
>
> >     I read the Intel IA-32 developer's manual recently, and I found
> > the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
> > wide, but the thing make me confused is that the default value
> > CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
> > not 6?   Any expanation about this would be appreciated!
>
>
> I don't recall seeing an answer to this.
> Was there one?
>
> Cheers,
> -- Jamie
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