On Wed, 2003-08-06 at 11:31, Zwane Mwaikambo wrote:
> The intel manual (10-36 Memory Cache Control - vol3) actually recommends
> the following procedure I was a bit anal about explicitely setting and
> clearing flags and used the specific TLB flush via cr3->reg->cr3. John
> could you give this a spin on your afflicted systems?
I'm not quite sure I follow. Really I've never looked at the mtrr code
before, so forgive my daftness. I just found a deadlock that was
locking my box caused by the synchronization between ipi_handler() and
set_mtrr() (which Mark's patch seems to properly fix).
How does this change affect the deadlock? Is this just a separate issue?
thanks
-john
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