[PATCH] [RESEND] Use of Performance Monitoring Counters based on Model number

From: Pallipadi, Venkatesh (venkatesh.pallipadi@intel.com)
Date: Tue Jul 29 2003 - 13:15:10 EST


Attaching a modified version of this patch, based on the feedback that I
got for my previous post.

Feedback and Resolution:
1) If you're going to do this you should fix up arch/i386/oprofile/ to
error out similarly at least
- Done. Made a similar change in oprofile code. Infact it already had a
check for 0xf, 0x3. Added one for 0x6, 0xd.

2) How about some macros for those magic numbers?
#define INTEL_MODEL_THINGABABOBBERPERON 0xd
- Not sure whether I need to add macros for family and models. We don't
seem to have macros for them anywhere else in kernel code.

3) It'd also be nice to let the user know why things aren't working
instead of silent failure.
- Done. Added a message while in nmi_init.

Let me know if you have any questions. Please Apply.

Thanks,
-Venkatesh

> -----Original Message-----
> From: Pallipadi, Venkatesh
> Sent: Wednesday, July 16, 2003 10:08 AM
> To: 'torvalds@osdl.org'
> Cc: 'linux-kernel@vger.kernel.org'; Mallick, Asit K
> Subject: [PATCH] Use of Performance Monitoring Counters based
> on Model number
>
>
>
>
> Attached is a small patch to make Linux kernel use of
> performance monitoring MSRs based on known processor models.
> Future processor implementation models may not support the
> same MSR layout.
>
> Please apply.
>
> Thanks,
> -Venkatesh

--- linux-2.6.0-test1/arch/i386/kernel/nmi.c.orig 2003-07-13
20:34:40.000000000 -0700
+++ linux-2.6.0-test1/arch/i386/kernel/nmi.c 2003-07-17
17:26:45.000000000 -0700
@@ -162,9 +162,15 @@
         case X86_VENDOR_INTEL:
                 switch (boot_cpu_data.x86) {
                 case 6:
+ if (boot_cpu_data.x86_model > 0xd)
+ break;
+
                         wrmsr(MSR_P6_EVNTSEL0, 0, 0);
                         break;
                 case 15:
+ if (boot_cpu_data.x86_model > 0x3)
+ break;
+
                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
                         break;
@@ -348,9 +354,19 @@
         case X86_VENDOR_INTEL:
                 switch (boot_cpu_data.x86) {
                 case 6:
+ if (boot_cpu_data.x86_model > 0xd) {
+ printk (KERN_INFO "Performance Counter
support for this CPU model not yet added.\n");
+ return;
+ }
+
                         setup_p6_watchdog();
                         break;
                 case 15:
+ if (boot_cpu_data.x86_model > 0x3) {
+ printk (KERN_INFO "Performance Counter
support for this CPU model not yet added.\n");
+ return;
+ }
+
                         if (!setup_p4_watchdog())
                                 return;
                         break;
--- linux-2.6.0-test1/arch/i386/oprofile/nmi_int.c.orig 2003-07-17
17:20:30.000000000 -0700
+++ linux-2.6.0-test1/arch/i386/oprofile/nmi_int.c 2003-07-17
17:21:06.000000000 -0700
@@ -285,6 +285,9 @@
 {
         __u8 cpu_model = current_cpu_data.x86_model;
 
+ if (cpu_model > 0xd)
+ return 0;
+
         if (cpu_model > 5) {
                 nmi_ops.cpu_type = "i386/piii";
         } else if (cpu_model > 2) {

-
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