From: Anton Blanchard <anton@samba.org>
Date: Sat, 14 Jun 2003 10:55:34 +1000
What I think is happening is that we arent tripping the prefetch
logic. We should take a latency hit for only the first cacheline
at which point the host bridge decides to start prefetching for
us. If not then we take take the latency hit on each transaction.
It sounds like what happens is that the sub-cacheline word reads
don't trigger the prefetch, but the first PCI read multiple
transaction does.
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