From: Hugh Dickins <hugh@veritas.com>
Date: Tue, 12 Nov 2002 06:53:04 +0000 (GMT)
Thanks for shedding light on that; but I'm still wondering if there
might be data loss if userspace modifies the page in the tiny window
between correctly positioned flush_cache_page and pte invalidation?
The flush merely writes back the data, a copy-back operation, fully L2
cache coherent. All cpus will see correct data if an intermittant
store occurs.
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