Re: [PATCH] Athlon cache-line fix

From: Akira Tsukamoto (akira-t@suna-asobi.com)
Date: Sat Nov 02 2002 - 22:26:13 EST

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On Sat, 2 Nov 2002 23:09:45 +0000
Andrew Kanaber <akanaber@chiark.greenend.org.uk> mentioned:
> Akira Tsukamoto wrote:
> > For Athlon CPU, CONFIG_X86_MK7,
> > the X86_L1_CACHE_SHIFT is set to 6, 128 Bytes
>
> Eh? L1_CACHE_BYTES is defined as (1 << L1_CACHE_SHIFT) in
> include/asm-i386/cache.h, which makes for a cache line size of 64 bytes
> which is right. Perhaps you were assuming the cache line size was
> 2 << L1_CACHE_SHIFT ?

Yes, it is 32bytes. :)
I think I was not sleeping right.

> Interesting that it increases
> performance (on at least one benchmark) though.

I also tried many times and it increases performace.

-- Akira Tsukamoto <akira-t@suna-asobi.com, at541@columbia.edu>

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