Consider an exception handler like vector 7, device_not_available:
ENTRY(device_not_available)
pushl $-1 # mark this as an int
SAVE_ALL
movl %cr0, %eax
testl $0x4, %eax # EM (math emulation bit)
jne device_not_available_emulate
preempt_stop
Since this is invoked via a trap gate and not an interrupt gate,
what's preventing this code from being preempted and resumed on
another CPU before the read from %cr0? Another example is the
machine_check vector (also trap gate) whose handlers access MSRs.
I'm sure this actually works, but I don't see how.
/Mikael
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Thu Oct 31 2002 - 22:00:49 EST