On Thu, 2002-10-03 at 13:40, Mikael Pettersson wrote:
> You just triggered Intel's "Unsynchronised Cross-Modifying Code
> Operations Can Cause Unexpected Instruction Execution Results"
> Erratum, which affects _every_ multiprocessor Intel P6 box.
> It's Pentium 3 Erratum E49 if you want to look it up; the other
> Intel P6s have it too, but with different numbers.
>
> In short, the only safe way to do this sort of thing is to force
> all other processors to wait on a barrier first, then modify the
> code, then release the barrier.
You must also ensure that the code you are modifying isnt on an IRQ path
(if it is you must do spin locks and then be very careful about cross
cpu tlb deadlocks). Finally you have no choice but to ensure you never
use it on the NMI path
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This archive was generated by hypermail 2b29 : Mon Oct 07 2002 - 22:00:39 EST