On Mon, 16 Sep 2002, James Cleverdon wrote:
> For APICs, when two interrupts are present when interrupts are enabled, the
> one with the highest interrupt vector number will be taken first. Vectors
> are statically assigned to the PCI slots, starting at 0x40 or 0x41. So, the
Vectors start from 0x31. That's what IRQ 0 gets. The interval is 8, so
the following vectors are 0x39, 0x41, and so on.
> last PCI interrupt source in the MPS table will be the highest priority.
Not necessarily -- after reaching the reserved range, i.e. 0xef, the
allocation wraps around to the previous base plus one. So for the second
pass vectors start from 0x32, for the third -- 0x33, etc.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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