On Mon, 2002-08-19 at 19:21, Xuehua Chen wrote:
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?
Yes
> 2. Does the SMP kernel handle the cache coherence
> problem
The kernel has to manage side issues (TLB shootdown etc)
> 3. What should I do if both of them don't handle cache
> coherence.
Debug your code. It is possible you are hitting a kernel bug but its
extremely unlikely.
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This archive was generated by hypermail 2b29 : Fri Aug 23 2002 - 22:00:17 EST