torvalds@transmeta.com said:
> The gdt descriptor alignment really shouldn't matter, but that bogus
> GDT _size_ thing in the descriptor might do it.
I knowit shouldn't, all I can say is that it does for me.
> Right now it's set to be 0x8000, which is not a legal GDT size (it
> should be of the form n*8-1), and is nonsensical anyway (the comment
> says 2048 entries, but the fact is, we don't _have_ 2048 entries in
> there).
I fixed this as part of my cleanups, but it doesn't actually make a difference
to the voyagers. What kills them is either gdt not 8 bytes aligned in setup.S
or %cs above about 0x30 when going from real to protected mode (once in
protected mode, it will happily accept arbitrary descriptor values).
The attached patch should fix all of the issues in this thread
- Align boot time GDT on 16 byte boundary (per intel recommendation)
- Use minimal boot time GDT and switch to complex one after protected mode.
- intel recommended aligment of gdt_desc and idt_desc in boot/setup.S
- make the boot time gdt_desc have the correct length.
- intel recommended aligment of cpu_gdt_descr
- make cpu_gdt_table align exactly on a cache line
I really only care about the first two of these to boot my voyager systems,
but fixing all the others may help future proof us for later intel chips (at
least now we follow all of the intel guidelines).
James
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This archive was generated by hypermail 2b29 : Fri Aug 23 2002 - 22:00:14 EST