Re: PCI DMA to small buffers on cache-incoherent arch

From: Tom Rini (trini@kernel.crashing.org)
Date: Mon Jun 10 2002 - 14:26:54 EST


On Mon, Jun 10, 2002 at 12:21:44PM -0700, Roland Dreier wrote:
> >>>>> "Tom" == Tom Rini <trini@kernel.crashing.org> writes:
>
> Tom> SMP_CACHE_BYTES is non-sensical on 4xx (and 8xx) since they
> Tom> don't do SMP..
>
> True but <asm/cache.h> defines it anyway...

Right, to L1_CACHE_BYTES even. :) So we should probably use that
directly.

> of course it would be no
> problem to use L1_CACHE_BYTES and in fact that probably makes sense
> because we're talking about PPC-only macros (other arches would have
> their own definition).

Well, ARM (whom we (PPC)) borrowed some ideas from will set it to
L1_CACHE_BYTES too, from the sound of rmk. So it might even be
consistent among the non coherent processors. :)

-- 
Tom Rini (TR1265)
http://gate.crashing.org/~trini/
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/



This archive was generated by hypermail 2b29 : Sat Jun 15 2002 - 22:00:19 EST