On Mon, 2002-05-27 at 13:35, Terje Eggestad wrote:
> I'm a bit curious my self, in theory the IO_APIC should drastically
> reduce interrupt latency. An x86 has two interrupt pins, IRQ and NMI.
The APIC reduces processing overhead. The APIC bus on the pentium III is
pretty slow (I believe its a serial 4 wire bus or similar). On the
Athlon and Pentium IV it seems to be a lot faster.
In the case of a livelock the problem is probably the cost of handling
the IRQ and poking slowly at the chip. Latency is pretty immaterial here
compared with irq servicing overheads.
Alan
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