Ion Badulescu wrote:
>
> On Wed, 6 Mar 2002, Jeff Garzik wrote:
>
> > There is a bugfix, which I will make locally before submitting:
> > PCI_COMMAND_INVALIDATE should be enabled -after- messing with
> > PCI_CACHE_LINE_SIZE.
>
> I didn't find anything in the starfire chipset's documentation about this,
> so is there a deeper reason for this ordering? As far as I know, most if
> not all x86 PCI chipsets silently map MWI to MW, so it should only matter
> for non-x86 plaforms, right?
More PCI than a Starfire requirement.
And there are plenty of ia32 platforms that benefit from MWI, too.
Often its server mobos that support MWI, but some cheaper ones do too.
> And, in general, are there any other tricks one can do to speed up the PCI
> transactions on non-x86 platforms? I'm still getting occasional overruns
> on sparc64 (card receiving packets faster than it can push them over PCI),
> which is somewhat disturbing..
Dynamically tune your RX and TX DMA burst settings when you notice these
conditions... It is indeed possible to saturate PCI bus bandwidth.
Jeff
-- Jeff Garzik | Usenet Rule #2 (John Gilmore): "The Net interprets Building 1024 | censorship as damage and routes around it." MandrakeSoft | - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Thu Mar 07 2002 - 21:00:57 EST